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PK P�j\rU8 ioctl.hnu �[��� #include <asm-generic/ioctl.h> PK P�j\&�6 socket.hnu �[��� #include <asm-generic/socket.h> PK P�j\�͈tZ Z msr.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ #ifndef _ASM_X86_MSR_H #define _ASM_X86_MSR_H #ifndef __ASSEMBLY__ #include <linux/types.h> #include <linux/ioctl.h> #define X86_IOC_RDMSR_REGS _IOWR('c', 0xA0, __u32[8]) #define X86_IOC_WRMSR_REGS _IOWR('c', 0xA1, __u32[8]) #endif /* __ASSEMBLY__ */ #endif /* _ASM_X86_MSR_H */ PK P�j\����g g unistd.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ #ifndef _ASM_X86_UNISTD_H #define _ASM_X86_UNISTD_H /* x32 syscall flag bit */ #define __X32_SYSCALL_BIT 0x40000000 # ifdef __i386__ # include <asm/unistd_32.h> # elif defined(__ILP32__) # include <asm/unistd_x32.h> # else # include <asm/unistd_64.h> # endif #endif /* _ASM_X86_UNISTD_H */ PK P�j\E�6�� � mtrr.hnu �[��� /* SPDX-License-Identifier: LGPL-2.0+ WITH Linux-syscall-note */ /* Generic MTRR (Memory Type Range Register) ioctls. Copyright (C) 1997-1999 Richard Gooch This library is free software; you can redistribute it and/or modify it under the terms of the GNU Library General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This library is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Library General Public License for more details. You should have received a copy of the GNU Library General Public License along with this library; if not, write to the Free Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. Richard Gooch may be reached by email at rgooch@atnf.csiro.au The postal address is: Richard Gooch, c/o ATNF, P. O. Box 76, Epping, N.S.W., 2121, Australia. */ #ifndef _ASM_X86_MTRR_H #define _ASM_X86_MTRR_H #include <linux/types.h> #include <linux/ioctl.h> #include <linux/errno.h> #define MTRR_IOCTL_BASE 'M' /* Warning: this structure has a different order from i386 on x86-64. The 32bit emulation code takes care of that. But you need to use this for 64bit, otherwise your X server will break. */ #ifdef __i386__ struct mtrr_sentry { unsigned long base; /* Base address */ unsigned int size; /* Size of region */ unsigned int type; /* Type of region */ }; struct mtrr_gentry { unsigned int regnum; /* Register number */ unsigned long base; /* Base address */ unsigned int size; /* Size of region */ unsigned int type; /* Type of region */ }; #else /* __i386__ */ struct mtrr_sentry { __u64 base; /* Base address */ __u32 size; /* Size of region */ __u32 type; /* Type of region */ }; struct mtrr_gentry { __u64 base; /* Base address */ __u32 size; /* Size of region */ __u32 regnum; /* Register number */ __u32 type; /* Type of region */ __u32 _pad; /* Unused */ }; #endif /* !__i386__ */ struct mtrr_var_range { __u32 base_lo; __u32 base_hi; __u32 mask_lo; __u32 mask_hi; }; /* In the Intel processor's MTRR interface, the MTRR type is always held in an 8 bit field: */ typedef __u8 mtrr_type; #define MTRR_NUM_FIXED_RANGES 88 #define MTRR_MAX_VAR_RANGES 256 struct mtrr_state_type { struct mtrr_var_range var_ranges[MTRR_MAX_VAR_RANGES]; mtrr_type fixed_ranges[MTRR_NUM_FIXED_RANGES]; unsigned char enabled; unsigned char have_fixed; mtrr_type def_type; }; #define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg)) #define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1) /* These are the various ioctls */ #define MTRRIOC_ADD_ENTRY _IOW(MTRR_IOCTL_BASE, 0, struct mtrr_sentry) #define MTRRIOC_SET_ENTRY _IOW(MTRR_IOCTL_BASE, 1, struct mtrr_sentry) #define MTRRIOC_DEL_ENTRY _IOW(MTRR_IOCTL_BASE, 2, struct mtrr_sentry) #define MTRRIOC_GET_ENTRY _IOWR(MTRR_IOCTL_BASE, 3, struct mtrr_gentry) #define MTRRIOC_KILL_ENTRY _IOW(MTRR_IOCTL_BASE, 4, struct mtrr_sentry) #define MTRRIOC_ADD_PAGE_ENTRY _IOW(MTRR_IOCTL_BASE, 5, struct mtrr_sentry) #define MTRRIOC_SET_PAGE_ENTRY _IOW(MTRR_IOCTL_BASE, 6, struct mtrr_sentry) #define MTRRIOC_DEL_PAGE_ENTRY _IOW(MTRR_IOCTL_BASE, 7, struct mtrr_sentry) #define MTRRIOC_GET_PAGE_ENTRY _IOWR(MTRR_IOCTL_BASE, 8, struct mtrr_gentry) #define MTRRIOC_KILL_PAGE_ENTRY _IOW(MTRR_IOCTL_BASE, 9, struct mtrr_sentry) /* MTRR memory types, which are defined in SDM */ #define MTRR_TYPE_UNCACHABLE 0 #define MTRR_TYPE_WRCOMB 1 /*#define MTRR_TYPE_ 2*/ /*#define MTRR_TYPE_ 3*/ #define MTRR_TYPE_WRTHROUGH 4 #define MTRR_TYPE_WRPROT 5 #define MTRR_TYPE_WRBACK 6 #define MTRR_NUM_TYPES 7 /* * Invalid MTRR memory type. mtrr_type_lookup() returns this value when * MTRRs are disabled. Note, this value is allocated from the reserved * values (0x7-0xff) of the MTRR memory types. */ #define MTRR_TYPE_INVALID 0xff #endif /* _ASM_X86_MTRR_H */ PK P�j\�KN� � sgx.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ /* * Copyright(c) 2016-20 Intel Corporation. */ #ifndef _ASM_X86_SGX_H #define _ASM_X86_SGX_H #include <linux/types.h> #include <linux/ioctl.h> /** * enum sgx_page_flags - page control flags * %SGX_PAGE_MEASURE: Measure the page contents with a sequence of * ENCLS[EEXTEND] operations. */ enum sgx_page_flags { SGX_PAGE_MEASURE = 0x01, }; #define SGX_MAGIC 0xA4 #define SGX_IOC_ENCLAVE_CREATE \ _IOW(SGX_MAGIC, 0x00, struct sgx_enclave_create) #define SGX_IOC_ENCLAVE_ADD_PAGES \ _IOWR(SGX_MAGIC, 0x01, struct sgx_enclave_add_pages) #define SGX_IOC_ENCLAVE_INIT \ _IOW(SGX_MAGIC, 0x02, struct sgx_enclave_init) #define SGX_IOC_ENCLAVE_PROVISION \ _IOW(SGX_MAGIC, 0x03, struct sgx_enclave_provision) #define SGX_IOC_VEPC_REMOVE_ALL \ _IO(SGX_MAGIC, 0x04) #define SGX_IOC_ENCLAVE_RESTRICT_PERMISSIONS \ _IOWR(SGX_MAGIC, 0x05, struct sgx_enclave_restrict_permissions) #define SGX_IOC_ENCLAVE_MODIFY_TYPES \ _IOWR(SGX_MAGIC, 0x06, struct sgx_enclave_modify_types) #define SGX_IOC_ENCLAVE_REMOVE_PAGES \ _IOWR(SGX_MAGIC, 0x07, struct sgx_enclave_remove_pages) /** * struct sgx_enclave_create - parameter structure for the * %SGX_IOC_ENCLAVE_CREATE ioctl * @src: address for the SECS page data */ struct sgx_enclave_create { __u64 src; }; /** * struct sgx_enclave_add_pages - parameter structure for the * %SGX_IOC_ENCLAVE_ADD_PAGE ioctl * @src: start address for the page data * @offset: starting page offset * @length: length of the data (multiple of the page size) * @secinfo: address for the SECINFO data * @flags: page control flags * @count: number of bytes added (multiple of the page size) */ struct sgx_enclave_add_pages { __u64 src; __u64 offset; __u64 length; __u64 secinfo; __u64 flags; __u64 count; }; /** * struct sgx_enclave_init - parameter structure for the * %SGX_IOC_ENCLAVE_INIT ioctl * @sigstruct: address for the SIGSTRUCT data */ struct sgx_enclave_init { __u64 sigstruct; }; /** * struct sgx_enclave_provision - parameter structure for the * %SGX_IOC_ENCLAVE_PROVISION ioctl * @fd: file handle of /dev/sgx_provision */ struct sgx_enclave_provision { __u64 fd; }; /** * struct sgx_enclave_restrict_permissions - parameters for ioctl * %SGX_IOC_ENCLAVE_RESTRICT_PERMISSIONS * @offset: starting page offset (page aligned relative to enclave base * address defined in SECS) * @length: length of memory (multiple of the page size) * @permissions:new permission bits for pages in range described by @offset * and @length * @result: (output) SGX result code of ENCLS[EMODPR] function * @count: (output) bytes successfully changed (multiple of page size) */ struct sgx_enclave_restrict_permissions { __u64 offset; __u64 length; __u64 permissions; __u64 result; __u64 count; }; /** * struct sgx_enclave_modify_types - parameters for ioctl * %SGX_IOC_ENCLAVE_MODIFY_TYPES * @offset: starting page offset (page aligned relative to enclave base * address defined in SECS) * @length: length of memory (multiple of the page size) * @page_type: new type for pages in range described by @offset and @length * @result: (output) SGX result code of ENCLS[EMODT] function * @count: (output) bytes successfully changed (multiple of page size) */ struct sgx_enclave_modify_types { __u64 offset; __u64 length; __u64 page_type; __u64 result; __u64 count; }; /** * struct sgx_enclave_remove_pages - %SGX_IOC_ENCLAVE_REMOVE_PAGES parameters * @offset: starting page offset (page aligned relative to enclave base * address defined in SECS) * @length: length of memory (multiple of the page size) * @count: (output) bytes successfully changed (multiple of page size) * * Regular (PT_REG) or TCS (PT_TCS) can be removed from an initialized * enclave if the system supports SGX2. First, the %SGX_IOC_ENCLAVE_MODIFY_TYPES * ioctl() should be used to change the page type to PT_TRIM. After that * succeeds ENCLU[EACCEPT] should be run from within the enclave and then * %SGX_IOC_ENCLAVE_REMOVE_PAGES can be used to complete the page removal. */ struct sgx_enclave_remove_pages { __u64 offset; __u64 length; __u64 count; }; struct sgx_enclave_run; /** * typedef sgx_enclave_user_handler_t - Exit handler function accepted by * __vdso_sgx_enter_enclave() * @run: The run instance given by the caller * * The register parameters contain the snapshot of their values at enclave * exit. An invalid ENCLU function number will cause -EINVAL to be returned * to the caller. * * Return: * - <= 0: The given value is returned back to the caller. * - > 0: ENCLU function to invoke, either EENTER or ERESUME. */ typedef int (*sgx_enclave_user_handler_t)(long rdi, long rsi, long rdx, long rsp, long r8, long r9, struct sgx_enclave_run *run); /** * struct sgx_enclave_run - the execution context of __vdso_sgx_enter_enclave() * @tcs: TCS used to enter the enclave * @function: The last seen ENCLU function (EENTER, ERESUME or EEXIT) * @exception_vector: The interrupt vector of the exception * @exception_error_code: The exception error code pulled out of the stack * @exception_addr: The address that triggered the exception * @user_handler: User provided callback run on exception * @user_data: Data passed to the user handler * @reserved Reserved for future extensions * * If @user_handler is provided, the handler will be invoked on all return paths * of the normal flow. The user handler may transfer control, e.g. via a * longjmp() call or a C++ exception, without returning to * __vdso_sgx_enter_enclave(). */ struct sgx_enclave_run { __u64 tcs; __u32 function; __u16 exception_vector; __u16 exception_error_code; __u64 exception_addr; __u64 user_handler; __u64 user_data; __u8 reserved[216]; }; /** * typedef vdso_sgx_enter_enclave_t - Prototype for __vdso_sgx_enter_enclave(), * a vDSO function to enter an SGX enclave. * @rdi: Pass-through value for RDI * @rsi: Pass-through value for RSI * @rdx: Pass-through value for RDX * @function: ENCLU function, must be EENTER or ERESUME * @r8: Pass-through value for R8 * @r9: Pass-through value for R9 * @run: struct sgx_enclave_run, must be non-NULL * * NOTE: __vdso_sgx_enter_enclave() does not ensure full compliance with the * x86-64 ABI, e.g. doesn't handle XSAVE state. Except for non-volatile * general purpose registers, EFLAGS.DF, and RSP alignment, preserving/setting * state in accordance with the x86-64 ABI is the responsibility of the enclave * and its runtime, i.e. __vdso_sgx_enter_enclave() cannot be called from C * code without careful consideration by both the enclave and its runtime. * * All general purpose registers except RAX, RBX and RCX are passed as-is to the * enclave. RAX, RBX and RCX are consumed by EENTER and ERESUME and are loaded * with @function, asynchronous exit pointer, and @run.tcs respectively. * * RBP and the stack are used to anchor __vdso_sgx_enter_enclave() to the * pre-enclave state, e.g. to retrieve @run.exception and @run.user_handler * after an enclave exit. All other registers are available for use by the * enclave and its runtime, e.g. an enclave can push additional data onto the * stack (and modify RSP) to pass information to the optional user handler (see * below). * * Most exceptions reported on ENCLU, including those that occur within the * enclave, are fixed up and reported synchronously instead of being delivered * via a standard signal. Debug Exceptions (#DB) and Breakpoints (#BP) are * never fixed up and are always delivered via standard signals. On synchrously * reported exceptions, -EFAULT is returned and details about the exception are * recorded in @run.exception, the optional sgx_enclave_exception struct. * * Return: * - 0: ENCLU function was successfully executed. * - -EINVAL: Invalid ENCL number (neither EENTER nor ERESUME). */ typedef int (*vdso_sgx_enter_enclave_t)(unsigned long rdi, unsigned long rsi, unsigned long rdx, unsigned int function, unsigned long r8, unsigned long r9, struct sgx_enclave_run *run); #endif /* _ASM_X86_SGX_H */ PK P�j\ ��� vsyscall.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ #ifndef _ASM_X86_VSYSCALL_H #define _ASM_X86_VSYSCALL_H enum vsyscall_num { __NR_vgettimeofday, __NR_vtime, __NR_vgetcpu, }; #define VSYSCALL_ADDR (-10UL << 20) #endif /* _ASM_X86_VSYSCALL_H */ PK P�j\��n� param.hnu �[��� #include <asm-generic/param.h> PK P�j\���VE E posix_types_x32.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ #ifndef _ASM_X86_POSIX_TYPES_X32_H #define _ASM_X86_POSIX_TYPES_X32_H /* * This file is only used by user-level software, so you need to * be a little careful about namespace pollution etc. Also, we cannot * assume GCC is being used. * * These types should generally match the ones used by the 64-bit kernel, * */ typedef long long __kernel_long_t; typedef unsigned long long __kernel_ulong_t; #define __kernel_long_t __kernel_long_t #include <asm/posix_types_64.h> #endif /* _ASM_X86_POSIX_TYPES_X32_H */ PK P�j\�{CE E hw_breakpoint.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ /* */ PK P�j\�j��� � types.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef _ASM_X86_TYPES_H #define _ASM_X86_TYPES_H #include <asm-generic/types.h> #endif /* _ASM_X86_TYPES_H */ PK P�j\Xl] hwcap2.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef _ASM_X86_HWCAP2_H #define _ASM_X86_HWCAP2_H /* MONITOR/MWAIT enabled in Ring 3 */ #define HWCAP2_RING3MWAIT (1 << 0) /* Kernel allows FSGSBASE instructions available in Ring 3 */ #define HWCAP2_FSGSBASE BIT(1) #endif PK P�j\�!i| e820.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ #ifndef _ASM_X86_E820_H #define _ASM_X86_E820_H #define E820MAP 0x2d0 /* our map */ #define E820MAX 128 /* number of entries in E820MAP */ /* * Legacy E820 BIOS limits us to 128 (E820MAX) nodes due to the * constrained space in the zeropage. If we have more nodes than * that, and if we've booted off EFI firmware, then the EFI tables * passed us from the EFI firmware can list more nodes. Size our * internal memory map tables to have room for these additional * nodes, based on up to three entries per node for which the * kernel was built: MAX_NUMNODES == (1 << CONFIG_NODES_SHIFT), * plus E820MAX, allowing space for the possible duplicate E820 * entries that might need room in the same arrays, prior to the * call to sanitize_e820_map() to remove duplicates. The allowance * of three memory map entries per node is "enough" entries for * the initial hardware platform motivating this mechanism to make * use of additional EFI map entries. Future platforms may want * to allow more than three entries per node or otherwise refine * this size. */ #define E820_X_MAX E820MAX #define E820NR 0x1e8 /* # entries in E820MAP */ #define E820_RAM 1 #define E820_RESERVED 2 #define E820_ACPI 3 #define E820_NVS 4 #define E820_UNUSABLE 5 #define E820_PMEM 7 /* * This is a non-standardized way to represent ADR or NVDIMM regions that * persist over a reboot. The kernel will ignore their special capabilities * unless the CONFIG_X86_PMEM_LEGACY option is set. * * ( Note that older platforms also used 6 for the same type of memory, * but newer versions switched to 12 as 6 was assigned differently. Some * time they will learn... ) */ #define E820_PRAM 12 /* * reserved RAM used by kernel itself * if CONFIG_INTEL_TXT is enabled, memory of this type will be * included in the S3 integrity calculation and so should not include * any memory that BIOS might alter over the S3 transition */ #define E820_RESERVED_KERN 128 #ifndef __ASSEMBLY__ #include <linux/types.h> struct e820entry { __u64 addr; /* start of memory segment */ __u64 size; /* size of memory segment */ __u32 type; /* type of memory segment */ } __attribute__((packed)); struct e820map { __u32 nr_map; struct e820entry map[E820_X_MAX]; }; #define ISA_START_ADDRESS 0xa0000 #define ISA_END_ADDRESS 0x100000 #define BIOS_BEGIN 0x000a0000 #define BIOS_END 0x00100000 #define BIOS_ROM_BASE 0xffe00000 #define BIOS_ROM_END 0xffffffff #endif /* __ASSEMBLY__ */ #endif /* _ASM_X86_E820_H */ PK P�j\��{ { perf_regs.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ #ifndef _ASM_X86_PERF_REGS_H #define _ASM_X86_PERF_REGS_H enum perf_event_x86_regs { PERF_REG_X86_AX, PERF_REG_X86_BX, PERF_REG_X86_CX, PERF_REG_X86_DX, PERF_REG_X86_SI, PERF_REG_X86_DI, PERF_REG_X86_BP, PERF_REG_X86_SP, PERF_REG_X86_IP, PERF_REG_X86_FLAGS, PERF_REG_X86_CS, PERF_REG_X86_SS, PERF_REG_X86_DS, PERF_REG_X86_ES, PERF_REG_X86_FS, PERF_REG_X86_GS, PERF_REG_X86_R8, PERF_REG_X86_R9, PERF_REG_X86_R10, PERF_REG_X86_R11, PERF_REG_X86_R12, PERF_REG_X86_R13, PERF_REG_X86_R14, PERF_REG_X86_R15, /* These are the limits for the GPRs. */ PERF_REG_X86_32_MAX = PERF_REG_X86_GS + 1, PERF_REG_X86_64_MAX = PERF_REG_X86_R15 + 1, /* These all need two bits set because they are 128bit */ PERF_REG_X86_XMM0 = 32, PERF_REG_X86_XMM1 = 34, PERF_REG_X86_XMM2 = 36, PERF_REG_X86_XMM3 = 38, PERF_REG_X86_XMM4 = 40, PERF_REG_X86_XMM5 = 42, PERF_REG_X86_XMM6 = 44, PERF_REG_X86_XMM7 = 46, PERF_REG_X86_XMM8 = 48, PERF_REG_X86_XMM9 = 50, PERF_REG_X86_XMM10 = 52, PERF_REG_X86_XMM11 = 54, PERF_REG_X86_XMM12 = 56, PERF_REG_X86_XMM13 = 58, PERF_REG_X86_XMM14 = 60, PERF_REG_X86_XMM15 = 62, /* These include both GPRs and XMMX registers */ PERF_REG_X86_XMM_MAX = PERF_REG_X86_XMM15 + 2, }; #define PERF_REG_EXTENDED_MASK (~((1ULL << PERF_REG_X86_XMM0) - 1)) #endif /* _ASM_X86_PERF_REGS_H */ PK P�j\��x"